This work implements a distributed Union-Find decoder on FPGA, using massively parallel processing units to achieve sub-microsecond decoding time for surface codes. The architecture is designed to scale to larger code distances.
The decoder trades the exact MWPM objective for the lower complexity of Union-Find decoding. See the IEEE QCE 2023 paper and the Helios implementation.
Yue Wu
Senior Researcher
I build algorithms, hardware, and systems for real-time quantum error correction at Microsoft Azure Quantum.